1. Technical Field
The present invention relates to phase change memory devices, and more particularly, to a bottom electrode contact structure of a phase change memory device and a method for manufacturing the same.
2. Related Art
Generally semiconductor memory devices are divided into volatile memory devices and nonvolatile memory devices depending upon whether or not they hold data when the power supply is interrupted. Some typical representative volatile memory devices include DRAM devices and SRAM devices. A typical representative nonvolatile memory device includes a flash memory device. These types of volatile and nonvolatile memory devices function by exploiting a binary logic system of ‘0’s or ‘1’s depending upon whether or not they store electric charges at specific areas within these devices.
In recent times, a substantial amount of effort has been invested in the hopes of developing novel alternate memory devices that can provide most if not all of the advantages exhibited by devices such as nonvolatileness, random access, low power consumption, and high integration.
One new representative memory device developed in the hopes of achieving these needs and requirements is the phase change memory device. As stated above, the phase change memory device uses a phase change material that changes phases in response to being heated when electrical current passes through it. Generally, a phase change material made of germanium (Ge), stibium (Sb) and tellurium (Te), which are collectively referred to as GST, is used as the phase change material.
When the GST phase change material is in an amorphous state it exhibits a relatively high electric resistance. As the phase of the GST phase change material changes from the amorphous state to a more ordered crystalline state, the electric resistance across the GST phase change material decreases. Therefore, since the GST phase change material exhibits different electric resistance values as a function of the phase state, the GST phase change material can be exploited as a storage medium of a memory device which is responsive to differences in electric resistance.
Generally phase change memory devices are constructed to be supplied with heat that arises from bottom electrode contacts. Bottom electrode contacts are often formed of conductive nitrides such as titanium nitride (TiN). In this regard, in order to accomplish low power consumption, it is often necessary to decrease the diameter of the bottom electrode contacts. In conformity with this need bottom electrode contacts are currently formed having minimum diameters that can be obtained by lithographic equipment.
However, as is common in the conventional lithography, misalignment can occur when forming a mask for delimiting bottom electrodes, and critical dimension (CD) can vary due to the misalignment. This CD error can cause a problem in that precise contact between phase change layer patterns and the bottom electrode contacts cannot be ensured. As a result Joule's heat transfer and the phase change of a phase change layer are unlikely to be evenly implemented across the resultant memory device.
Under these circumstances, research has continued to develop a feasible methodology for decreasing the contact area between the phase change layer and the bottom electrode while being capable of minimizing CD error.
FIGS. 1A through 1E are sectional views illustrating the processes of a method for forming the bottom electrode contact of a conventional phase change memory device.
Referring to FIG. 1A, a first interlayer dielectric 20 is formed on a semiconductor substrate 10 having an impurity region 10a formed therein. Afterwards, a diode 25 is then formed in the first interlayer dielectric 20 in which the diode 25 is electrically connected with the impurity region 10a. An ohmic contact layer 30 is then formed on the upper surface of the diode 25. A second interlayer dielectric 40 is then formed on the first interlayer dielectric 20 and on the ohmic contact layer 30.
Referring to FIG. 1B, by etching a predetermined portion of the second interlayer dielectric 40 to expose the ohmic contact layer 30, a bottom electrode contact hole 41 is defined.
Referring to FIG. 1C, a bottom electrode contact layer 45 is deposited on the wall of the bottom electrode contact hole 41 and on the upper surface of the second interlayer dielectric 40. Thereupon, a buried layer 50 is formed on the bottom electrode contact layer 45 to fill the bottom electrode contact hole 41.
Referring to FIG. 1D, the buried layer 50 is CMPed (chemically and mechanically polished) to expose the second interlayer dielectric 40 by which a bottom electrode contact 45a is formed.
Referring to FIG. 1E, a phase change pattern 60 is then formed on the bottom electrode contact 45a. 
In more conventional methodologies, when etching through the second interlayer dielectric 40 process to define the bottom electrode contact hole 41, an etchant gas may not reach deep enough to expose a sufficiently large area of the bottom electrode contact hole 41. This may be due to the thickness of the second interlayer dielectric 40 and/or may be due to the small diameter of the bottom electrode contact hole 41. As a result the resultant bottom electrode contact hole 41 may have a diameter that is smaller at the lower end than at the upper end of the bottom electrode contact hole 41.
If the bottom electrode contact hole 41 has a diameter that is smaller at the lower end than at the upper end then the contact area between the bottom electrode contact 45a and the diode 25 is diminished. As a result the current drivability of the diode 25 can deteriorate. Due to this fact, the amount of current cannot be sufficiently supplied to the bottom electrode contact 45a. 
Also, in the case where transient etching is conducted to solve the problem, as the diameter at the upper end of the bottom electrode contact hole 41 increases, the area of the bottom electrode contact 45a, which undergoes a phase change between an amorphous state and a crystalline state, is also likely to be changed. Due to this fact, because set resistance and reset resistance increase, the characteristics of the phase change memory device can degrade.